Optimizing timing solutions for your SSD and persistent memory designsAdoption of the PCIe interface into solid state drives offers significant advantages over legacy SAS/SATA protocols, the largest of which is the ability to scale. Most data centers today are outfitted with compute and storage hardware using the PCIe Gen3 standard but will quickly migrate to PCIe Gen4 and then to Gen5. Each new generation of the PCIe standard doubles the data rate compared to the previous generation, which puts more strain on the performance specifications of the reference clocks supplied to the SerDes at each endpoint. As the leader in high performance timing solutions, and working group member of the PCI-SIG, Silicon Labs offers the industry's highest performance PCIe Gen3/4/5 clock generators, clock buffers, and programmable clock generators capable of delivering PCIe Gen3/4/5 clocks. Our solutions feature HCSL output drivers with on-chip termination capable of matching either 85ohm or 100ohm transmission lines, reducing the number of external components needed, saving PCB area and system-level cost.
- Timing solutions for PCIe SSDs and persistent memory solutions
Block Diagram (SSD and Memory)
Block Diagram (Flash Array Storage)
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