Si5345W

Wireless Jitter Attenuator, Jitter Cleaner Si5345W

The Si5345W is an ultra-low phase noise jitter attenuating clock multiplier optimized for wireless applications which demand the highest level of integration and phase noise performance with ultra-small form factor and power consumption. The Si5345W accepts 4 clock inputs ranging from 3.072 to 750 MHz and generates 10 clock outputs from 0.000001 to 491.52 MHz. Based on our 4th generation DSPLL technology, the device combines frequency synthesis and jitter attenuation in a highly integrated digital solution that eliminates the need for external VCXO and loop filter components. A low cost, fixed-frequency oscillator provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise. Learn more about wireless DSPLL technology.

For Si5345W Datasheet and Reference Manual, please contact sales.

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Specifications

Loop Bandwidth Min (Hz)
Temperature Range Min (°C) -40
Input Frequency 3.072
Package Type QFN64
Control I2C/SPI
Line Impedance Match 0
Clock Generators false
Jitter Attenuating Clocks true
Number of Outputs 10
Input Frequency Max (MHz) 750
Intel x86 Clocks false
Package Size (mm) 9x9
Description Wireless Jitter Attenuator
Frequency Reference
4G/LTE Wireless Clocks true
56G SerDes false
Ouput Format(s) CML; HCSL; LVCMOS; LVDS; LVPECL
VDDO (V) 1.8; 2.5; 3.3
VDD (V) 1.8; 2.5; 3.3
Jitter Recommended Range (fs) <
Phase Jitter (ps RMS) 0.15
PCI Express false
Spread Spectrum false
Synchronous Ethernet/1588 false
DSPLLs 1
Reference Inputs 4
Output Frequency 0.000001
Embedded Xtal false
Loop Bandwidth Max (Hz)
Temperature Range Max (°C) 85
Output Frequency Max 491.52
Loop Bandwidth Min (Hz)
Temperature Range Min (°C) -40
Input Frequency 3.072
Package Type QFN64
Control I2C/SPI
Line Impedance Match 0
Clock Generators false
Jitter Attenuating Clocks true
Number of Outputs 10
Input Frequency Max (MHz) 750
Intel x86 Clocks false
Package Size (mm) 9x9
Description Wireless Jitter Attenuator
Frequency Reference
4G/LTE Wireless Clocks true
56G SerDes false
Ouput Format(s) CML; HCSL; LVCMOS; LVDS; LVPECL
VDDO (V) 1.8; 2.5; 3.3
VDD (V) 1.8; 2.5; 3.3
Jitter Recommended Range (fs) <
Phase Jitter (ps RMS) 0.15
PCI Express false
Spread Spectrum false
Synchronous Ethernet/1588 false
DSPLLs 1
Reference Inputs 4
Output Frequency 0.000001
Embedded Xtal false
Loop Bandwidth Max (Hz)
Temperature Range Max (°C) 85
Output Frequency Max 491.52

Images & Diagrams

PRODUCT DOCUMENTS

QUALITY AND PACKAGING

Look up product's green / pb-free status and information on RoHS, REACH, Halogen Free, and PFIS.


Certificate of Conformance
Product

si5345w-d-evb

Si5345W Wireless Jitter Attenuating Clock Multiplier Evaluation Kit

The Si5345W-D-EVB makes it easy to move from ClockBuilder Pro device configuration to hands-on performance evaluation.

For Si5345W-D-EVB user guide and technical documents, please contact sales.

MSRP $300.00

cbprog-dongle

ClockBuilder Pro Field Programmer

When used with ClockBuilder Pro software, the ClockBuilder Pro Field Programmer makes it simple for systems designers to develop, program, and debug any Si534x/7x/8x/9x or Si5332/57 clock device “in-system,” or in one of the convenient QFN sockets. The field programmer supports I2C or SPI interfaces to the host system, and SPI to the field programmer's QFN socket boards.

MSRP $99.00

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