Si5396J

Si5396J High-Performance Clock Jitter Attenuator, Jitter Cleaner

The Si5396J 4 -output, ultra-high-performance jitter attenuator combines fourth-generation DSPLL and MultiSynth technologies to enable any-frequency clock generation and jitter attenuation for applications like 56G PAM4 SerDes requiring the highest level of jitter performance. The device has an ultra-low jitter of 69 fs and a frequency output range up to 720 MHz and delivers a 0.09 ps rms phase jitter performance with a 0 ppm error. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level. The Si5396J can be quickly and easily configured using ClockBuilder Pro software.

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Specifications

Loop Bandwidth Min (Hz)
Output Bin <
Temperature Range Min (°C) -40
Input Frequency 0.008
Package Type LGA44
Control I2C/SPI
Line Impedance Match 0
Clock Generators false
Jitter Attenuating Clocks true
Number of Outputs 4
Input Frequency Max (MHz) 750
Intel x86 Clocks false
Package Size (mm) 7x7
Description Dual PLL Jitter Attenuator
Frequency Reference Internal
4G/LTE Wireless Clocks false
56G SerDes false
Ouput Format(s) CML; HCSL; LVCMOS; LVDS; LVPECL
VDDO (V) 1.8; 2.5; 3.3
VDD (V) 1.8; 3.3
Jitter Recommended Range (fs) <
PCI Express false
Phase Jitter (ps RMS) 0.09
Spread Spectrum false
Synchronous Ethernet/1588 true
PLLs 2
DSPLLs 0
Reference Inputs 4
Output Frequency 0.0001
Embedded Xtal false
Loop Bandwidth Max (Hz)
Temperature Range Max (°C) 85
Output Frequency Max 720
Loop Bandwidth Min (Hz)
Output Bin <
Temperature Range Min (°C) -40
Input Frequency 0.008
Package Type LGA44
Control I2C/SPI
Line Impedance Match 0
Clock Generators false
Jitter Attenuating Clocks true
Number of Outputs 4
Input Frequency Max (MHz) 750
Intel x86 Clocks false
Package Size (mm) 7x7
Description Dual PLL Jitter Attenuator
Frequency Reference Internal
4G/LTE Wireless Clocks false
56G SerDes false
Ouput Format(s) CML; HCSL; LVCMOS; LVDS; LVPECL
VDDO (V) 1.8; 2.5; 3.3
VDD (V) 1.8; 3.3
Jitter Recommended Range (fs) <
PCI Express false
Phase Jitter (ps RMS) 0.09
Spread Spectrum false
Synchronous Ethernet/1588 true
PLLs 2
DSPLLs 0
Reference Inputs 4
Output Frequency 0.0001
Embedded Xtal false
Loop Bandwidth Max (Hz)
Temperature Range Max (°C) 85
Output Frequency Max 720

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PRODUCT DOCUMENTS

QUALITY AND PACKAGING

Look up product's green / pb-free status and information on RoHS, REACH, Halogen Free, and PFIS.


Certificate of Conformance
Product

si5396j-a-evb

Si5396 A/B/J/K 2-PLL, 4-Output Jitter Attenuator Evaluation Kit

The Si5396J-A-EVB makes it easy to move from ClockBuilder Pro device configuration to hands-on performance evaluation.

MSRP $600.00

cbprog-dongle

ClockBuilder Pro Field Programmer

When used with ClockBuilder Pro software, the ClockBuilder Pro Field Programmer makes it simple for systems designers to develop, program, and debug any Si534x/7x/8x/9x or Si5332/57 clock device “in-system,” or in one of the convenient QFN sockets. The field programmer supports I2C or SPI interfaces to the host system, and SPI to the field programmer's QFN socket boards.

MSRP $99.00

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