The Si5396L 12 -output, ultra-high-performance jitter attenuator combines fourth-generation DSPLL and MultiSynth technologies to enable any-frequency clock generation and jitter attenuation for applications like 56G PAM4 SerDes requiring the highest level of jitter performance. The device has an ultra-low jitter of 69 fs and a frequency output range up to 720 MHz and delivers a 0.09 ps rms phase jitter performance with a 0 ppm error. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level. The Si5396L can be quickly and easily configured using ClockBuilder Pro software.