Si53302-B-GM

Si53302-B-GM Any Format Clock Buffer

The Si53302-B-GM is a universal 2 : 10 low jitter clock buffer/level translator with a pin-selectable output clock signal format and divider selection. The Si53302-B-GM features a glitchless switching mux, making it ideal for redundant clocking applications. The Si53302-B-GM utilizes Silicon Laboratories' advanced CMOS technology to fanout 10 from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53302-B-GM features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry.

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Specifications

Output Bin >
Temperature Range Min (°C) -40
Package Type QFN44
Line Impedance Match 0
Universal Buffers true
Number of Inputs 2
Number of Outputs 10
Frequency Max 725
Frequency Min (MHz) 1
Package Size (mm) 7x7
Description Universal 2:10 Clock Buffer
VDDO (V) 1.8 V; 2.5 V; 3.3 V
Ouput Format(s) CML; HCSL; LVCMOS; LVDS; LVPECL
Additive Jitter (ps RMS) 0.05
VDD (V) 1.8 V; 2.5 V; 3.3 V
PCIe Compliant true
Feedback Path false
Single Ended Input false
LVCMOS Buffers false
Differential Buffers true
Dual false
Temperature Range Max (°C) 85
Zero Delay Buffers false
Output Bin >
Temperature Range Min (°C) -40
Package Type QFN44
Line Impedance Match 0
Universal Buffers true
Number of Inputs 2
Number of Outputs 10
Frequency Max 725
Frequency Min (MHz) 1
Package Size (mm) 7x7
Description Universal 2:10 Clock Buffer
VDDO (V) 1.8 V; 2.5 V; 3.3 V
Ouput Format(s) CML; HCSL; LVCMOS; LVDS; LVPECL
Additive Jitter (ps RMS) 0.05
VDD (V) 1.8 V; 2.5 V; 3.3 V
PCIe Compliant true
Feedback Path false
Single Ended Input false
LVCMOS Buffers false
Differential Buffers true
Dual false
Temperature Range Max (°C) 85
Zero Delay Buffers false

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Product

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