The Si5382A is an ultra-low phase noise jitter attenuating clock multiplier optimized for wireless applications which demand the highest level of integration and phase noise performance with ultra-small form factor and power consumption. The Si5382A accepts 4 clock inputs ranging from 0.008 to 750 MHz and generates 12 clock outputs from 0.000001 to 2949.12 MHz. Based on our 4th generation DSPLL technology, the device combines frequency synthesis and jitter attenuation in a highly integrated digital solution that eliminates the need for external VCXO and loop filter components. A low cost, fixed-frequency oscillator provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise. Learn more about wireless DSPLL technology.