HSTL Clock Buffers

Our HSTL Clock Buffers are low jitter non-PLL based fanout buffers offering industry-leading flexibility while delivering best-in-class performance with additive jitter as low as 150 fs-rms. The family utilizes Silicon Laboratories' advanced CMOS technology to fanout 8 clocks from 5 - 350 MHz with guaranteed low additive jitter, low skew and low propagation delay variability. The family features HSTL output buffers with minimal cross-talk and superior supply noise rejection, simplifying low jitter clock distribution in noisy environments.