SSTL Clock Buffers

Our SSTL clock buffers are low jitter non-PLL based fanout buffers with industry-leading flexibility and best-in-class performance. With additive jitter as low as 150 fs RMS, the devices feature SSTL output buffers with minimal cross-talk and superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Based on our advanced CMOS technology, the devices provide fanout 8 clocks from 5 - 350 MHz, with guaranteed low additive jitter, low skew and low propagation delay variability.