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Product Documents
Features
- Fully matched, with integrated 5 GHz PA with harmonic, LNA with bypass mode and SPDT switch
- Integrated, positive slope logarithmic power detector. Detector output reverts to high impedance when not in use.
- High-power and Power-save modes
- Transmit gain: 30 dB
- Receive gain: 11 dB
- Output power: +17.5 dBm, MCS7, HT20
- Output power: +16 dBm, MCS9, HT80
- Small, QFN (16-pin, 2.3 x 2.3 x 0.33 mm) package (MSL1, 260°C per JEDEC J-STD-020)
Images & Diagrams
Specifications
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- Frequency (GHz) Min.
- 5.15
-
- Frequency (GHz) Max.
- 5.85
-
- Typ. Current @ VDD = 3.3 V 17.5dBm (mA)
-
- Typ. Current @ VDD = 3.6 V 17.5dBm (mA)
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- Typ. Current @ VCC = 3.6 V (mA)
-
- Typ. POUT @ 3.0% EVM (dBm)
- 17.5 @ -30DB EVM
-
- Typ. Current @ VCC = 5 V (mA)
-
- 802.11 WLAN Standard
- ac
-
- Antenna Ports
- 1
-
- Architecture
- 5 GHZ FRONT END MODULE
-
- Typ. POUT @ 2.5% EVM (dBm)
- 16 @ -35DB EVM
-
- Typ. Current @ VCC = 3.3 V (mA)
- 200
-
- Typ. Tx Gain (dB)
- 30
-
- Typ. POUT (dBm)
-
- VDD (V)
-
- VCC (V)
- 3.3
-
- Package
- QFN, 16-pin
-
- Package (mm)
- 2.3 X 2.3 X 0.33
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