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Product Documents
Features
- Fully matched, with integrated 5 GHz PA with harmonic, LNA with bypass mode and SPDT switch
- Integrated, positive slope logarithmic power detector. Detector output reverts to high impedance when not in use.
- High-power and Power-save modes
- Transmit gain: 30 dB
- Receive gain: 11 dB
- Output power: +17.5 dBm, MCS7, HT20
- Output power: +16 dBm, MCS9, HT80
- Small, QFN (16-pin, 2.3 x 2.3 x 0.33 mm) package (MSL1, 260°C per JEDEC J-STD-020)
Images & Diagrams
Specifications
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- 5.15
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- 5.85
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- 17.5 @ -30DB EVM
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- ac
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- 1
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- 5 GHZ FRONT END MODULE
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- 16 @ -35DB EVM
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- 200
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- 30
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- 3.3
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- QFN, 16-pin
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- 2.3 X 2.3 X 0.33
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